Dual-Mode Reference-less Clock Data Recovery Algorithm
نویسندگان
چکیده
منابع مشابه
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The cor...
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ژورنال
عنوان ژورنال: Journal of the Institute of Electronics and Information Engineers
سال: 2016
ISSN: 2287-5026
DOI: 10.5573/ieie.2016.53.5.077